Sometimes you will have such a brilliant idea it will not be possible to realize it using standard design practices. In those situations you will require innovative solutions to get the most out of your hardware. This is our core business and what our team initially started with. Our broad knowledge allows us to seek solutions beyond the limits of usual methods and we can therefore create solutions with order of magnitude better performance compared to industry standard results.
By simply rewriting existing software code or even bringing in internal or external hardware assisted processing we can create a software that will squeeze the last breath of power out of you hardware. Some times we go as deep as tweaking a couple of assembler instructions to get a faster code.
In this area we are able to:
optimize current software
perform optimization of software by using hardware accelerators
offloading work to other processing units which are available in the system
We do have a good knowledge in:
parallel computing
multi-core processing
vectorization of the code
empowering specialized cores designed for specific tasks
In addition to performing optimizations on any CPU architecture we have specialized in Power architectures and NXP QuiccEngine/eRISC communication processors where we have great experiences and deep knowledge about internals of the processors which we can utilize in such a way that perfect load-balancing between main CPU and QuiccEngine/eRISC will be achieved. We can move portions of low level and very fast tasks from the main CPU into QuiccEngine/eRISC when necessary.
Very often we also decide to move a part of software functionality from the CPU into a FPGA which does the processing in parallel if it is seen such system partitioning will achieve better performance.
Many of our high-performance solutions since 2007 are based on multicore processing. We utilize:
OS based parallel processing
Hypervisor based parallel processing
Bare metal parallel processing (this technique is used to be able to take control of each instruction executed, taking into account CPU pipeline utilization, prediction hit ratio, memory access times and cache utilization)
We are always open for finding new ideas thereby not limiting ourselves to known solutions.